library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memoria is
Port ( direccion : in STD_LOGIC_VECTOR (11 downto 0);
output : out STD_LOGIC_VECTOR (81 downto 0));
end memoria;
architecture Behavioral of memoria is
begin
process(direccion)
begin
--	inst2  prueba vf1    liga12        EPC'3  PC3  ERA'3    RA3   EY'3   Y3   EX'3   X3  CBD'  AS'  R/W'  CRI'     CZ CV CC CN     B[9..0]9    HB' DUPA'   OEUPA'   UPA[9..0]9   WA' EA(2)  WB' EB(2)  selbus  selmux    

--end if;
end process;
end Behavioral;